Latch
• Asynchronous
• Level Sensitive
• Clock signal = Enable signal* = Latch Signal
o It is not apt to call it Clock; better call it Enable
o When ‘1’, Q changes when D changes
o When ‘0’, Q retains state
• Used as Mechanical Switch De-bouncer
• Processor ALE signal implemented using Latch
Flip Flop
• Edge Sensitive (Master-Slave Flip Flop)
• Clock signal = Enable signal* = Gating Signal
o When ‘1’, Q depends on D; Q doesn’t change till next Clock.
o When ‘0’, Q retains state
• All sequential logic implemented using Flip Flops
Filed under: Digital Electronics, Interview Questions
