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Compilation error at UVM factory registration macros

package simple_pkg;

import uvm_pkg::*;

`include “uvm_macros.svh”

class my_class extends uvm_object;

`uvm_object_utils(my_class)

function new(string name=””,int additional_arg);

super.new(name);

endfunction

endclass

endpackage

The above package seems to be syntactically correct. But compiler(Eg. Cadence irun) throws error.

Compilation error: `uvm_object_utils(my_class). Task/function call, or property/sequence instance does not specify all required formal arguments.

`uvm_object_utils macro tries to register with factory, where the function new doesn’t have additional args.

Compiler throws error due to ‘additional_arg’ to function new. Remove this and compilation error goes off.

Error message is not clear and seems irrelevant to the issue here – a disadvantage of using macros; the macro expands into something that we can’t visualize.

 

Summary: Avoid additional args to ‘new’ function when using UVM factory registration.

 

 


Filed under: Interview Questions, SystemVerilog Tagged: interview, SystemVerilog, UVM Image may be NSFW.
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