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Shell: No such file or directory, but the file exists
Example File: # File Name : tools.csh source $PROJ_DIR/scripts/getOS.csh Commands run from terminal: $> echo $SHELL tcsh $> pwd project1 $> cd work $> source ../tools.csh...
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Compilation error at UVM factory registration macros
package simple_pkg; import uvm_pkg::*; `include “uvm_macros.svh” class my_class extends uvm_object; `uvm_object_utils(my_class) function new(string name=””,int additional_arg); super.new(name);...
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Preprocess text with embedded perl code
Create my first project at Github: This script can be downloaded from https://github.com/agraja/text2perl/blob/master/text2perl.pl #!/usr/bin/perl # Tiny preprocessor: # Example: Paste this example in...
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Lambda Calculus in Perl
#!/usr/bin/perl # lambda expression = anonymous subroutine # all subroutines defined in this file are anonymous my $apply = sub { # lift my ($func,@args)=@_; sub {$func->(@args,@_)} # bind }; my...
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Identity Monad in Perl
#!/usr/bin/perl sub wrap_value { my $value=shift; return sub { return $value; }} sub bind_func { my ($value,$func)=@_; return $func->($value);} sub lift_func { my $func=shift; return sub { my...
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Preprocessor for Verilog, SystemVerilog
DownLoad PDF Version Here Contents Introduction Operation Syntax, Keywords Command Line options Example of input file Output of vpp.pl Complete script: vpp.pl Introduction This is a generic...
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Object Oriented Programming in Perl
Implementation of a Simple Tree Data Structure using OOP-Perl. Screenshot is used instead of text file for easy reading. Filed under: Bookmarks Tagged: array, bless, hash, lisp, module, oop, package,...
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SystemVerilog Array of Interfaces
// Viewing Array of interfaces in waveform viewer(dve) // Notes added inline in the below example interface my_if(input clk); logic [31:0] addr; logic [31:0] data; endinterface module dut(input xx,...
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General Purpose Preprocessor in Perl
Here is a preprocessor in perl, primarily for Verilog, SystemVerilog, but may be used for any language. There are programs with a lot of repetitive text. Language features like functions, objects can...
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Difference between reg, wire, logic in SystemVerilog
Wire Can be used for input, output, inout Multiple drivers, No drivers cause x Usage: Wire variable = value; Assign variable = value; Can be used to connect module instances Reg Can be used only for...
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Laptop plugged in, not charging
Laptop plugged in, but not charging: This was a really annoying issue, since I had bought the laptop just 3 months back. I searched in HP forums, (mine is a HP laptop), there were a range of...
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OOP Design Patterns Summary
Summary of OOPs Design Patterns from GoF Book Note: Syntax, keywords of C++ used in example snippets. Download: DesignPatterns_Summary Creational Patterns Singleton Object is created only once using a...
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Many-ism of System of Government
Democracy: Head of Government is elected by citizen’s votes. Dictatorship: No voting rights. Corrupt voting mechanism in Democracy leads to Dictatorship. Political Spectrum based on Economic Policy....
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List of Techniques to Generate Creative Ideas
6 Different Approaches to generate ideas 1. Extract the abstract: Simplify to a skeleton. Pay attention to details and classify. 2. Observe the features: Use SCAMPER on Attributes / Components /...
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Creativity can be taught
Everyone can be creative knowing these tools/tips. pdf Creativity Tools Quotes: Creativity can be taught. Anyone can create and innovate. Creativity is about generating new ideas. Innovation is about...
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SystemVerilog Interview Questions
What is the use of OOPs in Verification? Compare Verilog and SV. OOPs allows plug-and-play re-usable verification components Verilog – Procedural SystemVerilog – OOPs. Abstraction, Encapsulation,...
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Latch vs Flip Flop
Latch • Asynchronous • Level Sensitive • Clock signal = Enable signal* = Latch Signal o It is not apt to call it Clock; better call it Enable o When ‘1’, Q changes when D changes o When ‘0’, Q retains...
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Airtel Broadband connection on linux machine
I have a dual boot (Windows XP, openSUSE) PC. I have my airtel broadband connection activated. Airtel Engineer had done the setup and activation on WindowsXP. After he left, I did a reboot to openSUSE....
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System Verilog Singleton Example
Purpose of a singleton: To have a class which has only one instance(object) All the objects of this class refer to same global object that is created only once This design pattern provides a mechanism...
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C++ Singleton Example
Download here. singleton-design-pattern Purpose of a singleton: To have a class which has only one instance(object) All the objects of this class refer to same global object that is created only once...
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